View AD9238_3201339.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. AD9238 12-bit, 20/40/65 msps dual a/d converter features integrated dual 12-bit analog to digital converters single 3 v supply operation (2.7 v to 3.6 v) snr = 70 dbc (to nyquist, AD9238-65) sfdr = 85 dbc (to nyquist, AD9238-65) low power: 600 mw at 65 msps differential input with 500 mhz 3 db bandwidth on-chip reference and sha flexible analog input: 1 v p-p to 2 v p-p range offset binary or twos complement data format clock duty cycle stabilizer applications ultrasound equipment if sampling in communications receivers: is-95, cdma-one, imt-2000 battery-powered instruments hand-held scopemeters low cost digital oscilloscopes functional block diagram sha a/d sha a/d clock duty cycle stabilizer mode select oeb_a otr_a d11_a d0_a mux_select clk_a clk_b dcs dfs pdwn_a pdwn_b shared_ref oeb_b otr_b d11_b d0_b drgnd agnd drvdd avdd 0.5v vin+_a vin?_a reft_a refb_a vref sense agnd refb_b reft_b vin?_b vin+_b o/p buffers o/p buffers general description the AD9238 is a dual, 3 v, 12-bit, 20/40/65 msps analog-to- digital converter. it features dual high performance sample-and- hold amplifiers and an integrated voltage reference. the AD9238 uses a multistage differential pipelined architecture with output error correction logic to provide 12-bit accuracy and guarantee no missing codes over the full operating temperature range at up to 65 msps data rates. the wide bandwidth, differential sha allows for a variety of user selectable input ranges and offsets including single-ended applications. it is suitable for various applications including multiplexed systems that switch full-scale voltage levels in suc- cessive channels and for sampling inputs at frequencies well beyond the nyquist rate. the AD9238 is suitable for applica- tions in communications, imaging, and medical ultrasound. dual single-ended clock inputs are used to control all internal conversion cycles. a duty cycle stabilizer is available on the AD9238-65 and can compensate for wide variations in the clock duty cycle, allowing the converters to maintain excellent perfor- mance. the digital output data is presented in either straight binary or twos complement format. out-of-range signals indi- cate an overflow condition, which can be used with the most significant bit to determine low or high overflow. fabricated on an advanced cmos process, the AD9238 is available in a space saving 64-lead lqfp and is specified over the industrial temperature range (?0 c to +85 c). product highlights 1. integrated, dual version of the ad9235? 12-bit, 20 msps/40 msps/65 msps adc. 2. speed grade options of 20 msps, 40 msps, and 65 msps allow flexibility between power, cost, and performance to suit an application. 3. the AD9238 operates from a single 3 v power supply and features a separate digital output driver supply to accommo- date 2.5 v and 3.3 v logic families. 4. low power consumption: AD9238-65 operating at 65 msps consumes a low 600 mw. AD9238-40 operating at 40 msps consumes a low 330 mw. AD9238-20 operating at 20 msps consumes a low 180 mw. 5. the patented sha input maintains excellent performance for input frequencies up to 100 mhz and can be configured for single-ended or differential operation. 6. typical channel isolation of 80 db @ f in = 10 mhz. 7. the clock duty cycle stabilizer (AD9238-65 only) maintains performance over a wide range of clock duty cycles. 8. the otr output bits indicate when either input signal is beyond the selected input range. 9. multiplexed data output option enables single-port operation from either data port a or data port b.
rev. 0 ? AD9238?pecifications dc specifications test AD9238bst-20 AD9238bst-40 AD9238bst-65 parameter temp level min typ max min typ max min typ max unit resolution full vi 12 12 12 bits accuracy no missing codes guaranteed full vi 12 12 12 bits offset error full vi 0.30 1.2 0.50 1.1 0.50 1.1 % fsr gain error 1 full iv 0.30 2.2 0.50 2.4 0.50 2.5 % fsr differential nonlinearity (dnl) 2 full v 0.35 0.35 0.35 lsb 25 cv 0.35 0.9 0.35 0.8 0.35 1.0 lsb integral nonlinearity (inl) 2 full vi 0.45 0.60 0.70 lsb 25 ci 0.40 1.4 0.50 1.4 0.55 1.75 lsb temperature drift offset error full v 2 2 3 ppm/ c gain error 1 full v 12 12 12 ppm/ c internal voltage reference output voltage error (1 v mode) full vi 5 35 5 35 5 35 mv load regulation @ 1.0 ma full v 0.8 0.8 0.8 mv output voltage error (0.5 v mode) full v 2.5 2.5 2.5 mv load regulation @ 0.5 ma full v 0.1 0.1 0.1 mv input referred noise input span = 1 v 25 cv 0.54 0.54 0.54 lsb rms input span = 2.0 v 25 cv 0.27 0.27 0.27 lsb rms analog input input span = 1.0 v full iv 1 1 1 v p-p input span = 2.0 v full iv 2 2 2 v p-p input capacitance 3 full v 7 7 7 pf reference input resistance full v 7 7 7 k power supplies supply voltages avdd full iv 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 v drvdd full iv 2.25 3.0 3.6 2.25 3.0 3.6 2.25 3.0 3.6 v supply current iavdd 2 full v 60 110 200 ma idrvdd 2 full v 4 10 14 ma psrr full v 0.01 0.01 0.01 % fsr power consumption dc input 4 full v 180 330 600 mw sine wave input 2 full vi 190 212 360 397 640 698 mw standby power 5 full v 2.0 2.0 2.0 mw matching characteristics offset error full v 0.1 0.1 0.1 % fsr gain error full v 0.05 0.05 0.05 % fsr notes 1 gain error and gain temperature coefficient are based on the a/d converter only (with a fixed 1.0 v external reference). 2 measured at maximum clock rate with a low frequency sine wave input and approximately 5 pf loading on each output bit. 3 input capacitance refers to the effective capacitance between one differential input pin and avss. refer to figure 2 for the eq uivalent analog input structure. 4 measured with dc input at maximum clock rate. 5 standby power is measured with the clk_a and clk_b pins inactive (i.e., set to avdd or agnd). specifications subject to change without notice. (avdd = 3 v, drvdd = 2.5 v, maximum sample rate, clk_a = clk_b; ain = ?.5 dbfs differential input, 1.0 v internal reference, t min to t max , unless otherwise noted.)
rev. 0 AD9238 ? dc specifications test AD9238bst-20 AD9238bst-40 AD9238bst-65 parameter temp level min typ max min typ max min typ max unit logic inputs high level input voltage full iv 2.0 2.0 2.0 v low level input voltage full iv 0.8 0.8 0.8 v high level input current full iv ?0 +10 ?0 +10 ?0 +10 a low level input current full iv ?0 +10 ?0 +10 ?0 +10 a input capacitance full v 2 2 2 pf logic outputs * drvdd = 3.3 v high level output voltage full iv 3.29 3.29 3.29 v (ioh = 50 a) high level output voltage full iv 3.25 3.25 3.25 v (ioh = 0.5 ma) low level output voltage full iv 0.05 0.05 0.05 v (iol = 50 a) low level output voltage full iv 0.2 0.2 0.2 v (iol = 1.6 ma) drvdd = 2.5 v high level output voltage full iv 2.49 2.49 2.49 v (ioh = 50 a) high level output voltage full iv 2.45 2.45 2.45 v (ioh = 0.5 ma) low level output voltage full iv 0.05 0.05 0.05 v (iol = 50 a) low level output voltage full iv 0.2 0.2 0.2 v (iol = 1.6 ma) * output voltage levels measured with 5 pf load on each output. specifications subject to change without notice. switching specifications test AD9238bst-20 AD9238bst-40 AD9238bst-65 parameter temp level min typ max min typ max min typ max unit switching performance max conversion rate full vi 20 40 65 msps min conversion rate full v 1 1 1 msps clk period full v 50.0 25.0 15.4 ns clk pulsewidth high 1 full v 15.0 8.8 6.2 ns clk pulsewidth low 1 full v 15.0 8.8 6.2 ns data output parameters output delay 2 (t pd ) full v 3.5 3.5 3.5 ns pipeline delay (latency) full v 7 7 7 cycles aperture delay (t a ) full v 1.0 1.0 1.0 ns aperture uncertainty (t j ) full v 0.5 0.5 0.5 ps rms wake-up time 3 full v 2.5 2.5 2.5 ms out - of - range recovery time full v 1 1 2 cycles notes 1 the AD9238-65 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycle (see tpc 20 ). 2 output delay is measured from clock 50% transition to data 50% transition, with 5 pf load on each output. 3 wake-up time is dependent on value of decoupling capacitors, typical values shown with 0.1 f and 10 f capacitors on reft and refb. specifications subject to change without notice. n?1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 analog input clock data out n?9 n?8 n?7 n?6 n?5 n?4 n?3 n?2 n?1 n t od = 3.5ns typ figure 1. timing diagram (avdd = 3 v, drvdd = 2.5 v, maximum sample rate, clkin1 = clkin2; ain = ?.5 dbfs differential input, 1.0 v internal reference, t min to t max , unless otherwise noted.)
rev. 0 ? AD9238 ac specifications test AD9238bst-20 AD9238bst-40 AD9238bst-65 parameter temp level min typ max min typ max min typ max unit signal-to-noise ratio f input = 2.4 mhz 25 cv 70.4 70.4 70.3 dbc f input = 9.7 mhz full v 70.2 dbc 25 ci v 69.7 70.4 dbc f input = 19.6 mhz full v 70.1 dbc 25 ci v 69.7 70.3 dbc f input = 32.5 mhz full v 69.3 dbc 25 ci v 68.7 69.5 dbc f input = 100 mhz 25 cv 68.7 68.3 67.6 dbc signal-to-noise and distortion ratio f input = 2.4 mhz 25 cv 70.2 70.2 70.4 dbc f input = 9.7 mhz full v 70.1 dbc 25 ci v 69.3 70.2 dbc f input = 19.6 mhz full v 69.9 dbc 25 ci v 69.4 70.1 dbc f input = 32.5 mhz full v 68.9 dbc 25 ci v 68.1 69.1 dbc f input = 100 mhz 25 cv 67.9 67.9 66.6 dbc total harmonic distortion f input = 2.4 mhz 25 cv ?3.0 ?3.0 ?3.0 dbc f input = 9.7 mhz full v ?1.0 dbc 25 ci ?3.0 ?4.6 dbc f input = 19.6 mhz full v ?1.0 dbc 25 ci ?3.0 ?5.5 dbc f input = 32.5 mhz full v ?8.0 dbc 25 ci 8 0.0 ?1.7 dbc f input = 100 mhz 25 cv ?7.0 ?9.0 ?4.0 dbc worst harmonic (2nd or 3rd) f input = 9.7 mhz full v ?4.0 dbc f input = 19.6 mhz full v ?5.0 dbc f input = 32.5 mhz full v ?0.0 dbc spurious free dynamic range f input = 2.4 mhz 25 cv 86.0 86.0 86.0 dbc f input = 9.7 mhz full v 84.0 dbc 25 ci 76.1 86.0 dbc f input = 19.6 mhz full v 85.0 dbc 25 ci 76.7 86.0 dbc f input = 32.5 mhz full v 80.0 dbc 25 ci 72.5 83.0 dbc f input = 100 mhz 25 cv 79.0 81.0 75.0 dbc crosstalk full v ?0 ?0 ?0 db specifications subject to change without notice. (avdd = 3 v, drvdd = 2.5 v, maximum sample rate, clk_a = clk_b; ain = ?.5 dbfs differential input, 1.0 v internal reference, t min to t max , unless otherwise noted.)
rev. 0 AD9238 ? explanation of test levels i 100% production tested. ii 100% production tested at +25 c and sample tested at specified temperatures. iii sample tested only. iv parameter is guaranteed by design and characterization testing. v parameter is a typical value only. vi 100% production tested at +25 c; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices. ordering guide model temperature range package description package option AD9238bst-20 ?0 c to +85 c 64-lead low profile quad flat pack (lqfp) st-64 AD9238bst-40 ?0 c to +85 c 64-lead low profile quad flat pack (lqfp) st-64 AD9238bst-65 ?0 c to +85 c 64-lead low profile quad flat pack (lqfp) st-64 AD9238-20pcb evaluation board with AD9238bst-20 AD9238-40pcb evaluation board with AD9238bst-40 AD9238-65pcb evaluation board with AD9238bst-65 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD9238 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1 with respect pin name to min max unit electrical avdd agnd ?.3 +3.9 v drvdd drgnd ?.3 +3.9 v agnd drgnd ?.3 +0.3 v avdd drvdd ?.9 +3.9 v digital outputs drgnd ?.3 drvdd + 0.3 v clk, dcs, mux_select, shared_ref, oeb, dfs agnd ?.3 avdd + 0.3 v vina, vinb agnd ?.3 avdd + 0.3 v vref agnd ?.3 avdd + 0.3 v sense agnd ?.3 avdd + 0.3 v refb, reft agnd ?.3 avdd + 0.3 v pdwn agnd ?.3 avdd + 0.3 v environmental 2 operating temperature ?5 +85 c junction temperature +150 c lead temperature (10 sec) +300 c storage temperature ?5 +150 c notes 1 absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional oper- ability is not necessarily implied. exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 typical thermal impedances (64-lead lqfp); ja = 54 c/w. these measure- ments were taken on a 4-layer board in still air, in accordance with eia/jesd51-7.
rev. 0 ? AD9238 pin function descriptions pin no. name description 2 vin+_a analog input pin (+) for channel a 3v in?a analog input pin (? for channel a 15 vin+_b analog input pin (+) for channel b 14 vin?b analog input pin (? for channel b 6 reft_a differential reference (+) for channel a 7 refb_a differential reference (? for channel a 11 reft_b differential reference (+) for channel b 10 refb_b differential reference (? for channel b 8 vref voltage reference input/output 9 sense reference mode selection 18 clk_b clock input pin for channel b 63 clk_a clock input pin for channel a 19 dcs enable duty cycle stabilizer (dcs) mode 20 dfs data output format select bit (low for offset binary, high for twos complement) 21 pdwn_b power-down function selection for channel b (active high) 60 pdwn_a power-down function selection for channel a (active high) 22 oeb_b output enable bit for channel b 59 oeb_a output enable bit for channel a (low setting enables channel a output data bus) 44?1, 54?7 d0_a (lsb)?11_a (msb) channel a data output bits 25?7, 30?8 d0_b (lsb)?11_b (msb) channel b data output bits 39 otr_b out of range indicator for channel b 58 otr_a out of range indicator for channel a 62 shared_ref shared reference control bit (low for independent reference mode, high for shared reference mode) 61 mux_select data multiplexed mode (see description for how to enable; high setting disables output data multiplexed mode) 5, 12, 17, 64 avdd analog power supply 1, 4, 13, 16 agnd analog ground 28, 40, 53 drgnd digital output ground 29, 41, 52 drvdd digital output driver supply. must be decoupled to drgnd with a mini- mum 0.1 f capacitor. recommended decoupling is 0.1 f capacitor in parallel with 10 f. 23, 24, 42, 43 dnc do not connect pins. should be left floating. pin configuration 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 55 54 53 52 51 50 49 59 58 57 56 pin 1 identifier 64-lead lqfp top view (not to scale) d4_a d3_a d2_a d1_a d0_a dnc dnc drgnd otr_b d11_b (msb) d10_b d9_b d8_b d7_b d6_b AD9238 agnd avdd reft_a refb_a vref sense refb_b agnd vin?_b vin+_b vin+_a vin?_a avdd reft_b clk_a shared_ref mux_select oeb_a d11_a (msb) d10_a d9_a d8_a drgnd d7_a d6_a d5_a clk_b dcs dfs pdwn_b oeb_b dnc d0_b d1_b d2_b drgnd d3_b d4_b d5_b dnc agnd agnd avdd drvdd drvdd avdd pdwn_a otr_a drvdd dnc = do not connect
rev. 0 AD9238 ? avdd vin+_a, vin?_a, vin+_b, vin?_b, figure 2. equivalent analog input circuit drvdd d11_a ? d0_a d11_b ? d0_b otr_a, otr_b figure 3. equivalent digital output circuit avdd clk_a, clk_b dcs, dfs, mux_select shared_ref figure 4. equivalent digital input circuit
rev. 0 ? AD9238 definition of terms aperture delay aperture delay is a measure of the sample-and-hold amplifier (sha) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion. aperture jitter the variation in aperture delay for successive samples, which is manifested as noise on the input to the a/d converter. integral nonlinearity (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each particular code to the true straight line. differential nonlinearity (dnl, no missing codes) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes must be present over all operating ranges. offset error the major carry transition should occur for an analog value 1/2 lsb below vin+ = vin? offset error is defined as the devia- tion of the actual transition from that point. gain error the first code transition should occur at an analog value 1/2 lsb above negative full scale. the last transition should occur at an analog value 1 1/2 lsb below the nominal full scale. gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. temperature drift the temperature drift for zero error and gain error specifies the maximum change from the initial (25 c) value to the value at t min or t max . power supply rejection the specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. total harmonic distortion (thd) the ratio of the rms sum of the first six harmonic compo- nents to the rms value of the measured input signal and is expressed as a percentage or in decibels relative to the peak carrier signal (dbc). signal-to-noise and distortion (s/n+d, sinad) ratio the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/n+d is expressed in decibels relative to the peak carrier signal (dbc). effective number of bits (enob) using the following formula: enob sinad =? (.). 176 602 effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its mea- sured sinad . signal-to-noise ratio (snr) the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels relative to the peak carrier signal (dbc). spurious free dynamic range (sfdr) the difference in db between the rms amplitude of the input signal and the peak spurious signal. nyquist sampling when the frequency components of the analog input are below the nyquist frequency (f clock /2), this is often referred to as nyquist sampling. if sampling due to the effects of aliasing, an adc is not necessarily limited to nyquist sampling. higher sampled frequencies will be aliased down into the first nyquist zone (dc ?f clock /2) on the output of the adc. care must be taken that the bandwidth of the sampled signal does not overlap nyquist zones and alias onto itself. nyquist sampling performance is limited by the band- width of the input sha and clock jitter (jitter adds more noise at higher input frequencies). two-tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. out-of-range recovery time out-of-range recovery time is the time it takes for the a/d con- verter to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. crosstalk coupling onto one channel being driven by a (?.5 dbfs) signal when the adjacent interfering channel is driven by a full-scale signal. measurement includes all spurs resulting from both direct coupling and mixing components.
rev. 0 t ypical performance characteristics?d9238 ? ?120 10 15 20 25 30 5 0 ?100 ?80 ?60 ?40 ?20 0 second harmonic frequency ? mhz crosstalk magnitude ? dbfs third harmonic tpc 1. single-tone fft of channel a digitizing f in = 12.5 mhz while channel b is digitizing f in 10 mhz ?120 10 db 15 20 25 30 5 0 ?100 ?80 ?60 ?40 ?20 0 frequency ? hz crosstalk second harmonic tpc 2. single-tone fft of channel a digitizing f in = 70 mhz while channel b is digitizing f in 76 mhz ?120 10 db 15 20 25 30 5 0 ?100 ?80 ?60 ?40 ?20 0 second harmonic frequency ? hz crosstalk tpc 3. single-tone fft of channel a digitizing f in = 120 mhz while channel b is digitizing f in = 126 mhz adc sample rate ? msps 90 55 40 sfdr/snr ? dbc 85 80 75 70 65 60 45 50 55 60 65 95 100 snr sfdr 50 tpc 4. AD9238-65 single-tone snr/sfdr vs. fs with f in = 32.5 mhz adc sample rate ? msps 90 55 40 sfdr/snr ? dbc 85 80 75 70 65 60 95 100 snr sfdr 50 35 30 25 20 snr snr tpc 5. AD9238-40 single-tone snr/sfdr vs. fs with f in = 20 mhz adc sample rate ? msps 90 55 sfdr/snr ? dbc 85 80 75 70 65 60 95 100 50 0.00e + 00 5.00e + 00 1.00e + 01 1.50e + 01 2.00e + 01 sfdr snr tpc 6. AD9238-20 single-tone snr/sfdr vs. fs with f in = 10 mhz
rev. 0 ?0 AD9238 input amplitude ? dbfs 90 sfdr/snr ? dbc 80 70 60 100 snr sfdr 50 ?35 snr snr 40 ?30 ?25 ?20 ?15 ?10 ?5 0 tpc 7. AD9238-65 single-tone snr/sfdr vs. ain with f in = 32.5 mhz input amplitude ? dbfs 90 sfdr/snr ? dbc 80 70 60 100 snr sfdr 50 ?35 snr snr 40 ?30 ?25 ?20 ?15 ?10 ?5 0 tpc 8. AD9238-40 single-tone snr/sfdr vs. ain with f in = 20 mhz input amplitude ? dbfs 90 sfdr/snr ? dbc 80 70 60 100 snr sfdr 50 ?35 snr snr 40 ?30 ?25 ?20 ?15 ?10 ?5 0 tpc 9. AD9238-20 single-tone snr/sfdr vs. ain with f in = 10 mhz input frequency ? mhz 90 sfdr/snr ? dbc 85 80 75 95 snr sfdr 70 0 snr 65 20 40 60 80 100 120 140 tpc 10. AD9238-65 single-tone snr/sfdr vs. f in 90 85 80 75 95 snr sfdr 70 0 snr snr 65 20 40 60 80 100 120 140 input frequency ? mhz sfdr/snr ? dbc tpc 11. AD9238-40 single-tone snr/sfdr vs. f in 90 85 80 75 95 snr sfdr 70 0 snr snr 65 20 40 60 80 100 120 140 input frequency ? mhz sfdr/snr ? dbc tpc 12. AD9238-20 single-tone snr/sfdr vs. f in
rev. 0 AD9238 ?1 ?120 10 magnitude ? dbfs 15 20 25 30 5 0 ?100 ?80 ?60 ?40 ?20 0 frequency ? mhz tpc 13. dual-tone fft with f in 1 = 45 mhz and f in 2 = 46 mhz ?120 10 15 20 25 30 5 0 ?100 ?80 ?60 ?40 ?20 0 magnitude ? dbfs frequency ? mhz tpc 14. dual-tone fft with f in 1 = 70 mhz and f in 2 = 71 mhz ?120 10 15 20 25 30 5 0 ?100 ?80 ?60 ?40 ?20 0 magnitude ? dbfs frequency ? mhz tpc 15. dual-tone fft with f in 1 = 200 mhz and f in 2 = 201 mhz input amplitude ? dbfs 95 sfdr/snr ? dbfs 90 85 80 100 snr sfdr 75 ?24 snr snr 70 ?21 ?18 ?15 ?12 ?9 ?6 65 60 tpc 16. dual-tone snr/sfdr vs. ain with f in 1 = 45 mhz and f in 2 = 46 mhz input amplitude ? dbfs 95 sfdr/snr ? dbfs 90 85 80 100 snr sfdr 75 ?24 snr snr 70 ?21 ?18 ?15 ?12 ?9 ?6 65 60 tpc 17. dual-tone snr/sfdr vs. ain with f in 1 = 70 mhz and f in 2 = 71 mhz input amplitude ? dbfs 95 sfdr/snr ? dbfs 90 85 80 100 snr sfdr 75 ?24 snr 70 ?21 ?18 ?15 ?12 ?9 ?6 65 60 tpc 18. dual-tone snr/sfdr vs. ain with f in 1 = 200 mhz and f in 2 = 201 mhz
rev. 0 ?2 AD9238 clock frequency sinad ? dbc 72 70 74 0 68 20 40 60 sinad ?65 sinad ?40 sinad ?20 12 11.5 11 tpc 19. sinad vs. fs with nyquist input duty cycle ? % 85 sinad/sfdr ? dbc 80 75 70 95 65 30 60 40 45 50 55 60 65 55 50 dcs on ? sinad dcs on ? sfdr dcs off ? sinad dcs off ? sfdr 90 35 tpc 20. sinad/sfdr vs. clock duty cycle temperature ? c 80 sinad/sfdr ? db 78 76 74 84 72 ?50 70 050 100 68 66 sinad sfdr 82 tpc 21. sinad/sfdr vs. temperature with f in = 32.5 mhz sample rate ? msps 500 avdd power ? mw 400 300 200 600 100 0102030405060 ?65 ?40 ?20 tpc 22. analog power consumption vs. fs code 0.6 ?0.8 inl ? lsb 0.4 0.2 0 ?0.2 ?0.4 ?0.6 0.8 1.0 ?1.0 1500 1000 500 0 2000 2500 3000 3500 4000 tpc 23. AD9238-65 typical inl code 0.6 ?0.8 dnl ? lsb 0.4 0.2 0 ?0.2 ?0.4 ?0.6 0.8 1.0 ?1.0 1500 1000 500 0 2000 2500 3000 3500 4000 tpc 24. AD9238-65 typical dnl
rev. 0 AD9238 ?3 theory of operation the AD9238 consists of two high performance analog-to-digital converters (adcs) that are based on the ad9235 converter core. the dual adc paths are independent, except for a shared internal band gap reference source, v ref . each of the adc? paths consists of a proprietary front end sample-and-hold ampli- fier (sha) followed by a pipelined switched capacitor adc. the pipelined adc is divided into three sections, consisting of a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit flash. each stage provides sufficient overlap to correct for flash errors in the preceding stages. the quantized outputs from each stage are combined through the digital correction logic block into a final 12-bit result. the pipelined architecture per- mits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. sampling occurs on the rising edge of the respective clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc and a residual multiplier to drive the next stage of the pipeline. the residual multiplier uses the flash adc output to control a switched capacitor digital-to-analog converter (dac) of the same resolution. the dac output is subtracted from the stage? input signal and the residual is amplified (mul- tiplied) to drive the next pipeline stage. the residual multiplier stage is also called a multiplying dac (mdac). one bit of redundancy is used in each one of the stages to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the input stage contains a differential sha that can be config- ured as ac- or dc-coupled in differential or single-ended modes. the output-staging block aligns the data, carries out the error correction, and passes the data to the output buffers. the out- put buffers are powered from a separate supply, allowing adjustment of the output voltage swing. analog input the analog input to the AD9238 is a differential switched capacitor, sha, that has been designed for optimum perfor- mance while processing a differential input signal. the sha input accepts inputs over a wide common-mode range. an input common-mode voltage of midsupply is recommended to maintain optimal performance. the sha input is a differential switched capacitor circuit. in figure 5, the clock signal alternatively switches the sha between sample mode and hold mode. when the sha is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. a small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. also, a small shunt capacitor can be placed across the inputs to provide dynamic charging currents. this passive network will create a low-pass filter at the adc? input; therefore, the precise values are dependant on the appli- cation. in if undersampling applications, any shunt capacitors should be removed. in combination with the driving source impedance, they would limit the input bandwidth. for best dynamic performance, the source impedances driving vin+ and vin?should be matched such that common-mode settling errors are symmetrical. these errors will be reduced by the common-mode rejection of the adc. 5pf 5pf t t vin+ vin? c par t t h h c par figure 5. switched capacitor input an internal differential reference buffer creates positive and negative reference voltages, reft and refb, respectively, that define the span of the adc core. the output common-mode of the reference buffer is set to midsupply, and the reft and refb voltages and span are defined as follows: reft avdd v refb avdd v span reft refb v ref ref ref =+ () =? () = ? () = 12 12 22 / / it can be seen from the equations above that the reft and refb voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the v ref voltage. the internal voltage reference can be pin-strapped to fixed values of 0.5 v or 1.0 v, or adjusted within the same range as discussed in the internal reference connection section. maximum snr performance will be achieved with the AD9238 set to the largest input span of 2 v p-p. the rela- tive snr degradation will be 3 db when changing from 2 v p-p mode to 1 v p-p mode. the sha may be driven from a source that keeps the signal peaks within the allowable range for the selected reference volt- age. the minimum and maximum common-mode input levels are defined as follows: vcm min max = =+ v vcm avdd v ref ref 2 2 () the minimum common-mode input level allows the AD9238 to accommodate ground-referenced inputs. although optimum performance is achieved with a differential input, a single-ended source may be driven into vin+ or vin? in this configuration, one input will accept the signal, while the opposite input should be set to midscale by connecting it to an appropriate reference. for example, a 2 v p-p signal may be applied to vin+ while a 1 v reference is applied to vin? the AD9238 will then accept an input signal varying between 2 v and 0 v. in the single- ended configuration, distortion performance may degrade significantly as compared to the differential case. however, the effect will be less noticeable at lower input frequencies and in the lower speed grade models (AD9238-40 and AD9238-20). differential input configurations as previously detailed, optimum performance will be achieved while driving the AD9238 in a differential input configuration.
rev. 0 ?4 AD9238 for baseband applications, the ad8138 differential driver provides excellent performance and a flexible interface to the adc. the output common-mode voltage of the ad8138 is easily set to avdd/2, and the driver can be configured in a sallen key filter topology to provide band limiting of the input signal. at input frequencies in the second nyquist zone and above, the performance of most amplifiers will not be adequate to achieve the true performance of the AD9238. this is especially true in if undersampling applications where frequencies in the 70 mhz to 200 mhz range are being sampled. for these applications, differential transformer coupling is the recommended input configuration, as shown in figure 6. AD9238 vina vinb avdd agnd 2v p-p 50 50 10pf 10pf 49.9 1k 1k 0.1 f figure 6. differential transformer coupling the signal characteristics must be considered when selecting a transformer. most rf transformers will saturate at frequencies below a few mhz, and excessive signal power can also cause core saturation, which leads to distortion. single-ended input configuration a single-ended input may provide adequate performance in cost-sensitive applications. in this configuration, there will be a degradation in sfdr and in distortion performance due to the large input common-mode swing. however, if the source impedances on each input are matched, there should be little effect on snr performance. clock input and considerations typical high speed adcs use both clock edges to generate a variety of internal timing signals, and as a result may be sensitive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the AD9238 provides separate clock inputs for each channel. the optimum performance is achieved with the clocks operated at the same frequency and phase. clocking the channels asyn- chronously may degrade performance significantly. in some applications, it is desirable to skew the clock timing of adjacent channels. the AD9238? separate clock inputs allow for clock timing skew (typically 1 ns) between the channels without significant performance degradation. the AD9238-65 contains two clock duty cycle stabilizers, one for each converter that retime the nonsampling edge, providing an internal clock with a nominal 50% duty cycle (dcs is not available on the 40 msps or ?0 msps versions). input clock rates of over 40 mhz can use the dcs so that a wide range of input clock duty cycles can be accommodated. maintaining a 50% duty cycle clock is particularly important in high speed applications, when proper track-and-hold times for the con- verter are required to maintain high performance. the dcs can be enabled by tying the dcs pin high. the duty cycle stabilizer utilizes a delay locked loop to create the nonsampling edge. as a result, any changes to the sampling frequency will require approximately 2 to 3 microseconds to allow the dll to acquire and settle to the new rate. high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given full-scale input frequency (f input ) due only to aperture jitter (t j ) can be calculated with the following equation: snr f t input j degradation = [] 20 10 1 2 log / in the equation, the rms aperture jitter, t j , represents the root- sum-square of all jitter sources, which include the clock input, analog input signal, and adc aperture jitter specification. undersampling applications are particularly sensitive to jitter. the clock input is a digital signal that should be treated as an analog signal with logic level threshold voltages, especially in cases where aperture jitter may affect the dynamic range of the ad 9238. power supplies for clock drivers should be sepa- rated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter crystal controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or other meth- ods), it should be retimed by the original clock at the last step. power dissipation and standby mode the power dissipated by the AD9238 is proportional to its sam- pling rates. the digital (drvdd) power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. the digital drive current can be calculated by: ivcfn drvdd drvdd load clock = where n is the number of bits changing and c load is the aver- age load on the digital pins that changed. the analog circuitry is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption. each speed grade dissipates a baseline power at low sample rates that increases with clock frequency. either channel of the AD9238 can be placed in standby mode independently by asserting the pwdn_a or pdwn_b pin. it is recommended that the input clock(s) and analog input(s) remain static during either independent or total standby, which will result in a typical power consumption of 1 mw for the adc. note: if dcs is enabled, it is mandatory to disable the clock of an independently powered-down channel. otherwise, significant distortion will result on the active channel. if the clock inputs remain active while in total standby mode, the typical power dissipation of 12 mw will result. the minimum standby power is achieved when both channels are placed in full power-down mode (pdwn_a = pdwn_b = hi). under this condition, the internal references are powered down. when either or both of the channel paths are enabled after a power-down, the wake-up time will be directly related to the recharging of the reft and refb d ecoupling capacitors and the duration of the power-down. typically, it takes approxi- mately 5 ms to restore full operation with fully discharged 0.1 f and 10 f decoupling capacitors on reft and refb. a single channel can be powered down for moderate power savings. the powered-down channel shuts down internal circuits, but both the reference buffers and shared reference remain
rev. 0 AD9238 ?5 powered. because the buffer and voltage reference remain pow- ered, the wake-up time is reduced to several clock cycles. digital outputs the AD9238 output drivers can be configured to interface with 2.5 v or 3.3 v logic families by matching drvdd to the digital supply of the interfaced logic. the output drivers are sized to provide sufficient output current to drive a wide variety of logic families. however, large drive currents tend to cause current glitches on the supplies that may affect converter performance. applications requiring the adc to drive large capacitive loads or large fan-outs may require external buffers or latches. the data format can be selected for either offset binary or twos complement. this is discussed later in the data format section. timing the AD9238 provides latched data outputs with a pipeline delay of seven clock cycles. data outputs are available one propagation delay (t pd ) after the rising edge of the clock signal. refer to figure 1 for a detailed timing diagram. the internal duty cycle stabilizer can be enabled on the AD9238-65 using the dcs pin. this provides a stable 50% duty cycle to internal circuits. the length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9238. these transients can detract from the converter? dynamic performance. the lowest typical conversion rate of the AD9238 is 1 msps. at clock rates below 1 msps, dynamic performance may degrade. data format the AD9238 data output format can be configured for either twos complement or offset binary. this is controlled by the data format select pin (dfs). connecting dfs to agnd will produce offset binary output data. conversely, connecting dfs to avdd will format the output data as twos complement. the output data from the dual a/d converters can be multi- plexed onto a single 12-bit output bus. the multiplexing is accomplished by toggling the mux_select bit, which directs channel data to the same or opposite channel data port. when mux_select is logic high, the channel a data is directed to channel a output bus, and channel b data is directed to the channel b output bus. when mux_select is logic low, the channel data is reversed, i.e., channel a data is directed to chan- nel b out bus and channel b data is directed to the channel a output bus. by toggling the mux_select bit, multiplexed data is available on either of the output data ports. if the adcs are run with synchronized timing, this same clock can be applied to the mux_select bit. after the mux_select rising edge either data port will have the data for its respective channel, and after the falling edge the alternate channels data will be placed on the bus. typically, the other unused bus would be disabled by setting the appropriate oeb high to reduce power consumption and noise. figure 7 shows an example of multi- plex mode. when multiplexing data, the data rate is two times the sample rate. voltage reference a stable and accurate 0.5 v voltage reference is built into the AD9238. the input range can be adjusted by varying the refer- ence voltage applied to the AD9238, using either the internal reference with different external resistor configurations or an externally applied reference voltage. the input span of the adc tracks reference voltage changes linearly. if the adc is being driven differentially through a transformer, the reference voltage can be used to bias the center tap (com- mon-mode voltage). a shared reference mode allows the user to connect the references from the dual adcs together externally for superior gain and offset matching performance. if the adcs are to function independently, the reference decoupling can be treated independently and provide superior isolation between the dual channels. to enable the shared reference mode, the shared_ref pin must be tied high and external differential references must be externally shorted. (reft_a must be externally shorted to reft_b and refb_a must be shorted to refb_b.) b ?8 a ?7 b ?7 a ?6 b ?6 a ?5 b ?5 a ?4 b ?4 a ?3 b ?3 a ?2 b ?2 a ?1 b ?1 a 0 b 0 a 1 a ?1 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 b ?1 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 analog input adc a analog input adc b clk_a = clk_b = mux_select d0_a ?d11_a t odf t odr figure 7. example of multiplexed data format using the channel a output port and the same clock tied to clk_a, clk_b, and mux_select
rev. 0 ?6 AD9238 table i. reference configuration summary selected sense resulting resulting differential mode voltage v ref (v) span (v p-p) external reference avdd n/a 2 external reference internal fixed reference v ref 0.5 1.0 programmable reference 0.2 v to v ref 0.5 (1 + r2/r1) 2 v ref (see figure 7) internal fixed reference agnd to 0.2 v 1.0 2.0 internal reference connection a comparator within the AD9238 detects the potential at the sense pin and configures the reference into four possible states, which are summarized in table i. if sense is grounded, the reference amplifier switch is connected to the internal resis- tor divider (see figure 7), setting vref to 1 v. connecting the sense pin to vref switches the reference amplifier output to the sense pin, completing the loop and providing a 0.5 v reference output. if a resistor divider is connected as shown in figure 8, the switch will again be set to the sense pin. this will put the reference amplifier in a noninverting mode with the vref output defined as follows: vrr ref =+ 05 1 2 1 .( ) in all reference configurations, reft and refb drive the adc core and establish its input span. the input range of the adc always equals twice the voltage at the reference pin for either an internal or an external reference. vin+ vin? vref 10 f 10 f 0.1 f 0.1 f reft adc core select logic sense 0.1 f 0.5v AD9238 refb 0.1 f figure 8. internal reference configuration external reference operation the use of an external reference may be necessary to enhance the gain accuracy of the adc or to improve thermal drift char- ac teristics. when multiple adcs track one another, a single reference (internal or external) may be necessary to reduce gain matching errors to an acceptable level. a high precision external reference may also be selected to provide lower gain and offset temperature drift. figure 10 shows the typical drift characteris- tics of the internal reference in both 1 v and 0.5 v modes. when the sense pin is tied to avdd, the internal reference will be disabled, allowing the use of an external reference. an internal reference buffer will load the external reference with an equivalent 7 k load. the internal buffer will still generate the positive and negative full-scale references, reft and refb, for the adc core. the input span will always be twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of 1 v. if the internal reference of the AD9238 is used to drive multiple converters to improve gain matching, the loading of the refer- ence by the other converters must be considered. figure 11 depicts how the internal reference voltage is affected by loading. vin+ vin? vref 10 f 10 f 0.1 f 0.1 f reft adc core select logic sense 0.1 f 0.5v AD9238 refb 0.1 f r1 r2 figure 9. programmable reference configuration
rev. 0 AD9238 ?7 temperature ? c 0.2 v ref error ? % 1.2 1.0 0.8 0.6 0.4 0 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 v ref = 1v v ref = 0.5v figure 10. typical v ref drift load ? ma ?0.20 error ? % 0.05 0 ?0.05 ?0.10 ?0.15 ?0.25 0 0.5 1.0 1.5 2.0 2.5 3.0 0.5v error 1v error figure 11. v ref accuracy vs. load outline dimensions 64-lead quad flat pack [lqfp] (st-64) dimensions shown in millimeters top view (pins down) 1 16 17 33 32 48 49 64 0.23 0.18 0.13 0.40 bsc 7.00 bsc 1.60 max seating plane 0.75 0.60 0.45 view a 7 3.5 0 0.20 0.09 1.45 1.40 1.35 0.15 0.05 0.08 max coplanarity view a rotated 90 ccw seating plane 9.00 bsc compliant to jedec standards ms-026bbd
?8
?9
c02640??/03(0) printed in u.s.a. ?0

▲Up To Search▲

Price & Availability of AD9238

	To Download AD9238 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .